07308558 is referenced by 28 patents and cites 27 patents.

The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.

Title
Multiprocessor data processing system having scalable data interconnect and data routing mechanism
Application Number
10/752959
Publication Number
7308558 (B2)
Application Date
January 7, 2004
Publication Date
December 11, 2007
Inventor
Jody Bern Joyner
Austin
TX, US
Vicente Enrique Chung
Austin
TX, US
Jerry Don Lewis
Round Rock
TX, US
Ravi Kumar Arimilli
Austin
TX, US
Agent
Dillon & Yudell
Casimer K Salys
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 16/163
G06F 15/16
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