07276944 cites 9 patents.

A clock generation circuit and a clock generation method are provided, which are spread spectrum clock generation and accurate phase control of a reference clock signal and an output clock signal. An input divider unit 70 divides an input clock signal CLKR by 50 to output a divided input clock signal CLKS. A DLL circuit 80 operates to obtain delay control signals DCS1, DCS2. A modulation circuit 40 modulates, in response to the delay control signals DCS1, DCS2 and a modulation signal MOD output from a modulation control circuit 50, the divided input clock signal CLKS to output a modulation clock signal CLKN. A phase comparator 11 detects the phase difference between the modulation clock signal CLKN and a divided inner clock signal CLKM. A clock generation unit 20 generates an output clock signal CLKO having frequency corresponding to a phase difference signal from the phase comparator 11.

Title
Clock generation circuit and clock generation method
Application Number
11/312392
Publication Number
7276944 (B2)
Application Date
December 21, 2005
Publication Date
October 2, 2007
Inventor
Yukisato Miyazaki
Kasugai
JP
Agent
Arent Fox
Assignee
Fujitsu
JP
IPC
H03L 7/06
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