07269617 is referenced by 5 patents and cites 4 patents.

A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.

Title
Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry
Application Number
10/712500
Publication Number
7269617 (B1)
Application Date
November 12, 2003
Publication Date
September 11, 2007
Inventor
Robert L Pelt
San Jose
CA, US
Benjamin Esposito
Oviedo
FL, US
Agent
Robert R Jackson
Alexander Shvarts
Ropes & Gray
Assignee
Altera Corporation
CA, US
IPC
G06F 7/523
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