07249306 is referenced by 49 patents and cites 271 patents.

A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage device is adapted to output a plurality of data blocks in parallel. A data bus provides a data path wide enough to accommodate the parallel data blocks and is further coupled to a plurality of CRC cores coupled to the data bus, wherein CRC values are calculated for every combination of data blocks on the data bus. A multiplexer coupled to the CRC cores selects the output of one of the CRC cores based on the number of valid data blocks on the data bus. Once the correct CRC value has been calculated, it is appended to a data segment, comprised of a group of data blocks, for transmission to another device.

Title
System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
Application Number
10/783345
Publication Number
7249306 (B2)
Application Date
February 20, 2004
Publication Date
July 24, 2007
Inventor
Addison Chen
Honolulu
HI, US
Agent
Zilka Kotab PC
Assignee
NVIDIA Corporation
CA, US
IPC
H03M 13/00
View Original Source