07243275 is referenced by 110 patents and cites 15 patents.

A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

Title
Smart verify for multi-state memories
Application Number
11/304961
Publication Number
7243275 (B2)
Application Date
December 14, 2005
Publication Date
July 10, 2007
Inventor
Yupin Kawing Fong
Fremont
CA, US
Daniel C Guterman
Fremont
CA, US
Geoffrey S Gongwer
Los Altos
CA, US
Agent
Davis Wright Tremaine
Assignee
SanDisk Corporation
CA, US
IPC
G11C 7/00
G11C 29/00
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