07242216 is referenced by 49 patents and cites 113 patents.

Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Embedding memory between tile arrangement of a configurable IC
Application Number
Publication Number
7242216 (B1)
Application Date
March 15, 2005
Publication Date
July 10, 2007
Jason Redgrave
Mountain View, 94040
Herman Schmit
Palo Alto, 94303
Adeli Law Group
H03K 19/177
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