07209996 is referenced by 43 patents and cites 9 patents.

In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.

Title
Multi-core multi-thread processor
Application Number
10/272786
Publication Number
7209996 (B2)
Application Date
October 16, 2002
Publication Date
April 24, 2007
Inventor
Michael K Wong
San Mateo
CA, US
Kunle A Olukotun
Stanford
CA, US
Leslie D Kohn
Fremont
CA, US
Agent
Martine Penilla & Gencarella
Assignee
Sun Microsystems
CA, US
IPC
G06F 13/16
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