07205185 is referenced by 15 patents and cites 16 patents.

A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

Title
Self-aligned planar double-gate process by self-aligned oxidation
Application Number
10/663471
Publication Number
7205185 (B2)
Application Date
September 15, 2003
Publication Date
April 17, 2007
Inventor
Erin Catherine Jones
Corvallis
OR, US
MeiKei Ieong
Wappingers Falls
NY, US
Suryanarayan G Hegde
Hollowville
NY, US
Kathryn W Guarini
Yorktown Heights
NY, US
Bruce B Doris
Brewster
NY, US
Omer H Dokumaci
Wappingers Falls
NY, US
Agent
Ido Tuchman Esq
Scully Scott Murphy & Presser P C
Assignee
International Busniess Machines Corporation
NY, US
IPC
H01L 21/8234
H01L 21/336
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