07202124 is referenced by 43 patents and cites 32 patents.

A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over the tensilely strained gettering layer. Additionally, the donor wafer may possess a particle-confining region proximate the tensilely strained layer. The method also includes introducing particles into the donor wafer to a depth below the surface, and accumulating at least some particles within the tensilely strained gettering layer. Next, the method includes initiating a cleaving action so as to separate at least one of the material layers form the substrate. The tensilely strained gettering layer may accumulate particles and/or point defects and reduce the implantation dose and thermal budget required for cleaving.

Title
Strained gettering layers for semiconductor processes
Application Number
10/956481
Publication Number
7202124 (B2)
Application Date
October 1, 2004
Publication Date
April 10, 2007
Inventor
Arthur J Pitera
Cambridge
MA, US
Eugene A Fitzgerald
Windham
NH, US
Agent
Wolf Greenfield & Sacks P C
Assignee
Massachusetts Institute of Technology
MA, US
IPC
H01L 21/322
H01L 21/8238
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