07199024 is referenced by 151 patents and cites 36 patents.

There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Title
Method of manufacturing a semiconductor device
Application Number
10/759297
Publication Number
7199024 (B2)
Application Date
January 20, 2004
Publication Date
April 3, 2007
Inventor
Shunpei Yamazaki
Setagaya
JP
Agent
Robinson Intellectual Property Law Office P C
Eric J Robinson
Assignee
Semiconductor Energy Laboratory
JP
IPC
H01L 21/46
H01L 21/30
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