07185426 is referenced by 258 patents and cites 125 patents.

A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.

Title
Method of manufacturing a semiconductor package
Application Number
10/806640
Publication Number
7185426 (B1)
Application Date
March 23, 2004
Publication Date
March 6, 2007
Inventor
Sukianto Rusli
Phoenix
AZ, US
Ronald Patrick Huemoeller
Chandler
AZ, US
David Jon Hiner
Chandler
AZ, US
Agent
Serge J Hodgson
Gunnison McKay & Hodgson L
Assignee
Amkor Technology
AZ, US
IPC
H05K 3/30
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