07184313 is referenced by 29 patents and cites 291 patents.

The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.

Title
Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
Application Number
11/155252
Publication Number
7184313 (B2)
Application Date
June 17, 2005
Publication Date
February 27, 2007
Inventor
Eduardo Maayan
Kfar Saba
IL
Yair Sofer
Tel-Aviv
IL
Yoram Betser
Mazkeret Batya
IL
Agent
Eitan Law Group
Assignee
Saifun Semiconductors
IL
IPC
G11C 16/04
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