07183650 is referenced by 20 patents and cites 11 patents.

A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.

Title
Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate
Application Number
10/483175
Publication Number
7183650 (B2)
Application Date
July 12, 2002
Publication Date
February 27, 2007
Inventor
Shigehisa Motowaki
Hitachi
JP
Takao Miwa
Hitachi
JP
Toshiya Sato
Hitachi
JP
Tadanori Segawa
Hitachi
JP
Ken Takahashi
Hitachi
JP
Daigoro Kamoto
Hitachi
JP
Hiroki Yamamoto
Hitachi
JP
Takashi Naito
Hitachi
JP
Yasutaka Suzuki
Hitachi
JP
Takashi Namekawa
Hitachi
JP
Takao Ishikawa
Hitachi
JP
Osamu Shiono
Hitachi
JP
Agent
Dickstein Shapiro
Assignee
Renesas Technology
JP
IPC
H01L 23/053
H01L 23/21
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