07174520 is referenced by 253 patents and cites 91 patents.

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Title
Characterization and verification for integrated circuit designs
Application Number
10/321283
Publication Number
7174520 (B2)
Application Date
December 17, 2002
Publication Date
February 6, 2007
Inventor
Taber H Smith
Fremont
CA, US
David White
Cambridge
MA, US
Agent
Bingham McCutchen
Assignee
Praesagus
MA, US
IPC
G21K 5/00
G03F 1/00
G06F 19/00
G06F 17/50
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