07170807 is referenced by 299 patents and cites 231 patents.

A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Title
Data storage device and refreshing method for use with such device
Application Number
11/48387
Publication Number
7170807 (B2)
Application Date
February 1, 2005
Publication Date
January 30, 2007
Inventor
Serguei Okhonin
Lausanne
CH
Pierre Fazan
Morges
CH
Agent
Neil A Steinberg
Assignee
Innovative Silicon
CH
IPC
G11C 11/34
G11C 11/24
G11C 7/00
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