07162612 is referenced by 4 patents and cites 22 patents.

An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus, and translates each of the macro instructions into associated native instructions for execution. If a first form of a first macro instruction is retrieved, the instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register. The bypass logic is coupled to the instruction translation logic. The bypass logic accesses the first bit within the control register to determine if the native bypass mode has been enabled, and detects wrapper macro instructions and, upon detection of the wrapper macro instructions, disables the instruction translation logic, and provides the native instructions for execution by the microprocessor, thereby bypassing the instruction translation logic.

Title
Mechanism in a microprocessor for executing native instructions directly from memory
Application Number
10/761845
Publication Number
7162612 (B2)
Application Date
January 21, 2004
Publication Date
January 9, 2007
Inventor
Terry Parks
Austin
TX, US
Arturo Martin de Nicolas
Austin
TX, US
G Glenn Henry
Austin
TX, US
Agent
James W Huffman
Richard K Huffman
Assignee
IP First
CA, US
IPC
G06F 5/00
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