07142623 is referenced by 40 patents and cites 9 patents.

An integrated circuit is operable to measure tolerance to jitter in a data stream signal. A Clock And Data Recovery Circuit (“CDR”) thereon recovers a phase of a clock for sampling a data stream signal containing a repeatable known sequence of data values and then samples the data stream signal with the recovered clock phase to obtain data stream sample data. An error rate determination circuit independently generates the repeatable known sequence of data values and compares them with the data stream sample data to determine an associated error rate. A control circuit coupled to the CDR delays the recovered clock phase by a predetermined amount a plurality of times and monitors the error rate after each time it delays the recovered clock phase. In this way, a maximum delayed clock phase is determined, representing a right timing signal margin for which the data stream signal can be sampled.

On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit
Application Number
Publication Number
7142623 (B2)
Application Date
May 31, 2002
Publication Date
November 28, 2006
Michael A Sorna
Hopewell Junction
Daryl K Neff Esq
International Business Machines Corporation
H03D 3/24
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