07129571 is referenced by 31 patents and cites 14 patents.

A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

Title
Semiconductor chip package having decoupling capacitor and manufacturing method thereof
Application Number
10/977533
Publication Number
7129571 (B2)
Application Date
October 28, 2004
Publication Date
October 31, 2006
Inventor
Sun Won Kang
Seoul
KR
Agent
Marger Johnson & McCollom P C
Assignee
Samsung Electronics
KR
IPC
H01L 23/02
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