07085153 is referenced by 167 patents and cites 245 patents.

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

Title
Semiconductor memory cell, array, architecture and device, and method of operating same
Application Number
10/829877
Publication Number
7085153 (B2)
Application Date
April 22, 2004
Publication Date
August 1, 2006
Inventor
Michel Bron
Lausanne
CH
Eric Carman
Cernex
FR
Serguei Okhonin
Lausanne
CH
Richard Ferrant
Esquibien
FR
Agent
Neil A Steinberg
Assignee
Innovative Silicon
CH
IPC
G11C 11/24
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