07065633 is referenced by 82 patents and cites 209 patents.

A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may be initiated under the CISC operating system. The exception may be delivered to the initiated thread for handling by the CISC operating system.

Title
System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
Application Number
9/626325
Publication Number
7065633 (B1)
Application Date
July 26, 2000
Publication Date
June 20, 2006
Inventor
Korbin S Van Dyke
Sunol
CA, US
Dale R Jurich
Los Gatos
CA, US
Sandeep Nijhawan
San Jose
CA, US
Matthew F Storch
Redwood City
CA, US
John S Yates Jr
Needham
MA, US
Agent
Willkie Farr & Gallagher
David E Boundy
Assignee
ATI International
BB
IPC
G06F 9/00
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