Breakpoint method for parallel hardware threads in multithreaded processor United States Patent 07020871

07020871 is referenced by 36 patents and cites 249 patents.

A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.

Title
Breakpoint method for parallel hardware threads in multithreaded processor
Application Number
9/747019
Publication Number
7020871 (B2)
Application Date
December 21, 2000
Publication Date
March 28, 2006
Inventor
Richard D Muratori
Stow
MA, US
James D Guilford
Northborough
MA, US
Donald F Hooper
Shrewsbury
MA, US
Desmond R Johnson
Rutland
MA, US
Serge Kornfeld
Westborough
MA, US
Debra Bernstein
Sudbury
MA, US
Agent
Fish & Richardson P C
Assignee
Intel Corporation
CA, US
IPC
G06F 9/44
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Citations: 36 (view full list)

  1. Nils Endric Schubert, Kenneth S McElvain, John Mark Beardslee, Mario Larouche: Enhanced hardware debugging with embedded FPGAS in a hardware description language. Synopsys, Blakely Sokoloff Taylor & Zafman, November 2, 2010: US07827510 (35 worldwide citation)
  2. Gilbert Wolrich, Matthew J Adiletta, William R Wheeler, Debra Bernstein, Donald F Hooper: Register set used in multithreaded parallel processor architecture. Intel Corporation, Fish & Richardson P C, June 9, 2009: US07546444 (27 worldwide citation)
  3. Gilbert Wolrich, Matthew Adiletta, William R Wheeler: Processor having a dedicated hash unit integrated within. Intel Corporation, June 22, 2010: US07743235 (14 worldwide citation)
  4. Jonathan David Bennett, Jane Chi Yan Fung, Grace Hai Yan Lo, William Gerald O Farrell: Breakpoint management and reconciliation for embedded scripts in a business integration language specified program process. International Business Machines Corporation, Monica Rooney Esq, Steven M Greenberg Esq, Carey Rodriguez Greenberg & Paul, December 30, 2008: US07472378 (14 worldwide citation)
  5. Kenn R Luecke: Methods and systems for mapping threads to processor cores. The Boeing Company, Armstrong Teasdale, September 3, 2013: US08527970 (11 worldwide citation)
  6. Lucian Codrescu, William C Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen: Embedded trace macrocell for enhanced digital signal processor debugging operations. QUALCOMM Incorporated, Peter Michael Kamarchik, Nicholas J Pauley, Jonathan T Velasco, December 25, 2012: US08341604 (8 worldwide citation)
  7. Lucian Codrescu, William C Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen: Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor. QUALCOMM Incorporated, Peter M Kamarchik, Nicholas J Pauley, Jonathan T Velasco, February 5, 2013: US08370806 (7 worldwide citation)
  8. Lucian Codrescu, William C Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen: Method and system for a digital signal processor debugging during power transitions. QUALCOMM Incorporated, Peter M Kamarchik, Nicholas J Pauley, Sam Talpalatsky, February 2, 2010: US07657791 (7 worldwide citation)
  9. Yan Li, Qi Yao, Weiying Yu, Yong Zheng: Method and system for debugging a program in a multi-thread environment. International Business Machines Corporation, Grasso PLLC, Fred Grasso, June 12, 2012: US08201152 (7 worldwide citation)
  10. Gilbert Wolrich, Matthew J Adiletta, William R Wheeler, Debra Bernstein, Donald F Hooper: Branch instruction for processor with branching dependent on a specified bit in a register. Intel Corporation, Fish & Richardson P C, September 2, 2008: US07421572 (6 worldwide citation)

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