07020017 is referenced by 357 patents and cites 42 patents.

Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Title
Variable programming of non-volatile memory
Application Number
10/818597
Publication Number
7020017 (B2)
Application Date
April 6, 2004
Publication Date
March 28, 2006
Inventor
Chi Ming Wang
Fremont
CA, US
Jian Chen
San Jose
CA, US
Agent
Vierra Magen Marcus Harmon & DeNiro
Assignee
Sandisk Corporation
CA, US
IPC
G11C 16/04
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