07016794 is referenced by 45 patents and cites 37 patents.

A method for analyzing electromigration and voltage drop effects in wire segments forming a power-bus grid of an integrated circuit. A floor plan design is created by mapping wire segments to various metal layers in the IC core. Digital, analog, and memory power zones indicating the power consumption of regions within the core are also mapped to the core. An equivalent circuit of the floor plan is generated in a netlist. The netlist is simulated, with the current density and voltage drop of power-bus wire segments calculated. Calculated current density and voltage drop values are analyzed in the floor plan design using a color map to indicate the current density and voltage drop levels of the wire segments. The designer can modify the floor plan design quickly and easily if the calculated current density and voltage drop values indicate potential electromigration or voltage drop problems.

Title
Floor plan development electromigration and voltage drop analysis tool
Application Number
9/268902
Publication Number
7016794 (B2)
Application Date
March 16, 1999
Publication Date
March 21, 2006
Inventor
Richard T Schultz
Fort Collins
CO, US
Agent
Christopher P Maiorana P C
Assignee
LSI Logic Corporation
CA, US
IPC
G06F 9/44
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