07001836 is referenced by 1 patents and cites 7 patents.

A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features a two step procedure for removal of insulator stop layers, wherein the stop layers are employed to allow selective dry etch procedures to be used for definition of both the via opening component and the trench shape component of the dual damascene opening. After definition of the via opening, terminating at the top surface of an underlying, first silicon nitride stop layer, a photoresist shape is used as an etch mask to allow a dry etch procedure to define a trench shape in a top portion of an insulator stack, with the dry etch procedure terminating at the top surface of an overlying second silicon nitride stop layer. The dry etch procedure also results in formation of a photoresist plug in the via hole, located on an underlying, first silicon nitride stop layer. The portion of the second silicon nitride stop layer exposed in the trench shape opening is next selectively removed via a first procedure of the two step, dry etch removal procedure, followed by removal of the trench shape defining photoresist shape and of the photoresist plug. Another dry etch procedure, the second step of the two step dry etch removal procedure, is next performed to selectively remove the portion of underlying, first silicon nitride stop layer exposed in the via opening, resulting in exposure of a portion of the top surface of the conductive structure. The two step, stop layer removal procedure reduces the level of insulator corner rounding at the top of the dual damascene opening, while also reducing damage to the top surface of the underlying conductive structure, exposed at the bottom of the dual damascene opening.

Title
Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers
Application Number
10/808802
Publication Number
7001836 (B2)
Application Date
March 25, 2004
Publication Date
February 21, 2006
Inventor
Shu Huei Suen
Hsinchu
TW
Fu Kai Yang
Shulin
TW
Assignee
Taiwan Semiconductor Manufacturing Company
TW
IPC
H01L 21/4763
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