06983456 is referenced by 86 patents and cites 22 patents.

A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

Title
Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
Application Number
10/285299
Publication Number
6983456 (B2)
Application Date
October 31, 2002
Publication Date
January 3, 2006
Inventor
Jeffrey Paul Brooks
St. Louis
MN, US
David Barker
Salinas
CA, US
Jon Steidel
Minneapolis
MN, US
Lisa Krause
Minneapolis
MN, US
Jeffrey Hammes
Colorado Springs
CO, US
Daniel Poznanovic
Colorado Springs
CO, US
Agent
Hogan & Hartson
William J Kubida
Peter J Meza
Assignee
SRC Computers
CO, US
IPC
G06F 9/44
View Original Source