06977930 is referenced by 91 patents and cites 22 patents.

A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path consists of a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus and congestion avoidance and dequeue management hardware. The architecture of the present invention has the advantages of high throughput and the ability to rapidly implement new features and capabilities.

Title
Pipelined packet switching and queuing architecture
Application Number
9/503552
Publication Number
6977930 (B1)
Application Date
February 14, 2000
Publication Date
December 20, 2005
Inventor
Michael Laor
Zichron-Yaakov
IL
Garry P Epps
Sunnyvale
CA, US
Agent
Campbell Stephenson Ascolese
Assignee
Cisco Technology
CA, US
IPC
H04L 012/56
H04L 012/28
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