06976194 is referenced by 68 patents and cites 64 patents.

A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to memory, where the memory includes a plurality of memory devices arranged on a plurality of memory modules. Each of the plurality of memory modules includes a plurality of the plurality of memory devices. The check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block. The plurality of check bits are defined to provide at least detection of a failure of one of the plurality of memory modules. The check/correct circuit is coupled to receive the encoded data block from the memory, and is configured to detect the failure of one of the plurality of memory modules responsive to decoding the encoded data block.

Title
Memory/Transmission medium failure handling controller and method
Application Number
10/184674
Publication Number
6976194 (B2)
Application Date
June 28, 2002
Publication Date
December 13, 2005
Inventor
Robert E Cypher
Saratoga
CA, US
Agent
Meyertons Hood Kivlin Kowert & Goetzel P C
Lawrence J Merkel
Assignee
Sun Microsystems
CA, US
IPC
G11C 029/00
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