06976095 is referenced by 40 patents and cites 208 patents.

A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from ports in segments and each segment is assigned to one of the program threads. Ordering of segments within packets, and between packets from the same port, is maintained by a scheduler program thread. The scheduler program thread blocks a new assignment of the previously assigned port to a program thread until the program thread to which the port was previously assigned has indicated that it has completed the processing of the segment from that port.

Title
Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
Application Number
9/476303
Publication Number
6976095 (B1)
Application Date
December 30, 1999
Publication Date
December 13, 2005
Inventor
Matthew J Adiletta
Worc
MA, US
Debra Bernstein
Sudbury
MA, US
Gilbert Wolrich
Framingham
MA, US
Agent
Fish & Richardson P C
Assignee
Intel Corporation
CA, US
IPC
G06F 015/16
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