06975016 is referenced by 165 patents and cites 43 patents.

A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Title
Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
Application Number
10/66643
Publication Number
6975016 (B2)
Application Date
February 6, 2002
Publication Date
December 13, 2005
Inventor
R Scott List
Beaverton
OR, US
Sarah E Kim
Portland
OR, US
Scot A Kellar
Bend
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G01R 001/073
B23K 019/00
H01L 029/06
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