06957402 is referenced by 180 patents and cites 6 patents.

A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard cells are made available to the circuit designer. Each different design may address a different problem associated with different manufacturing processes or a different design related yield limiter. Each of the design variants is characterized indicating its relative ease of manufacture, or it's yield sensitivity to certain IC design factors. The designer, typically with assistance from computer aided tools, can then select the standard cell variant for each of the cell used in the IC design that best addresses his or her design constraints. In other embodiments, variant versions of I/O cells and memory cells could also be created and made available to the designer in a similar fashion.

Title
Yield maximization in the manufacture of integrated circuits
Application Number
10/671029
Publication Number
6957402 (B2)
Application Date
September 24, 2003
Publication Date
October 18, 2005
Inventor
Dhrumil Gandhi
Cupertino
CA, US
Mark Templeton
Los Altos
CA, US
Agent
Martine Penilla & Gencarella
Assignee
Artisan Components
CA, US
IPC
G06F 017/50
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