06956284 is referenced by 61 patents and cites 113 patents.

The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

Title
Integrated circuit stacking system and method
Application Number
10/814532
Publication Number
6956284 (B2)
Application Date
March 31, 2004
Publication Date
October 18, 2005
Inventor
James Douglas Wehrly Jr
Austin
TX, US
David L Roper
Austin
TX, US
James Wilder
Austin
TX, US
James W Cady
Austin
TX, US
Agent
J Scott Denko
Andrews Kurth
Assignee
Staktek Group
TX, US
IPC
H01L 023/02
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