06954923 is referenced by 114 patents and cites 190 patents.

An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.

Title
Recording classification of instructions executed by a computer
Application Number
9/348317
Publication Number
6954923 (B1)
Application Date
July 7, 1999
Publication Date
October 11, 2005
Inventor
Korbin S Van Dyke
Sunol
CA, US
David L Reese
Westborough
MA, US
John S Yates Jr
Needham
MA, US
Agent
Willkie Farr & Gallagher
David E Boundy
Assignee
ATI International
BB
IPC
G06F 012/00
G06F 011/00
G06F 011/00
G06F 009/45
G06F 011/00
G06F 011/00
G06F 009/455
G06F 009/22
G06F 009/30
G06F 009/44
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