06928506 is referenced by 4 patents and cites 19 patents.

The invention relates to a circuit arrangement with two or more circuit sections, which cooperate through a data transfer device. The invention solves the problem of double area expenditure for two memory devices for each receiver, in that the data bus itself takes over the role of one of these memory devices, namely that of the memory device functioning as master. For this it is only necessary to integrate a single memory device on the data bus, which takes over the role of the no longer needed memory device for each data receiver. By saving the memory device associated with each receiver, the semiconductor chip area needed for communication buses can be optimized and the master memory device of the prior art may be replaced by the bus capacitance.

Title
Apparatus using bus capacitance to perform data storage during data transfer across the bus
Application Number
9/747279
Publication Number
6928506 (B2)
Application Date
December 21, 2000
Publication Date
August 9, 2005
Inventor
Michael Albert
Ettenheim
DE
Martin Czech
Freiburg
DE
Agent
O Shea Getz & Kosakowski P C
Assignee
Micronas
DE
IPC
G11C 011/24
G06F 013/14
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