06925424 is referenced by 120 patents and cites 2 patents.

A value in a counter on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in an accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator. In this way, a counter may be read, and its value, for the first thread, for example, remains consistent despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent way to update performance counts.

Title
Method, apparatus and computer program product for efficient per thread performance information
Application Number
10/687247
Publication Number
6925424 (B2)
Application Date
October 16, 2003
Publication Date
August 2, 2005
Inventor
Robert John Urquhart
Austin
TX, US
Luc Rene Smolders
Austin
TX, US
Frank Eliot Levine
Austin
TX, US
Scott Thomas Jones
Austin
TX, US
Agent
Anthony V S England
Diana Roberts Gerhardt
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 011/30
G06F 009/00
G06F 007/00
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