Enhancement of P-type metal-oxide-semiconductor field effect transistors United States Patent 06916727

06916727 is referenced by 9 patents and cites 81 patents.

Eugene Fitzgerald

A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.

Title
Enhancement of P-type metal-oxide-semiconductor field effect transistors
Application Number
10/177571
Publication Number
6916727 (B2)
Application Date
June 21, 2002
Publication Date
July 12, 2005
Inventor
Eugene A Fitzgerald
Windham
NH, US
Minjoo L Lee
Cambridge
MA, US
Christopher W Leitz
Nashua
NH, US
Agent
Testa Hurwitz & Thibeault
Assignee
Massachusetts Institute of Technology
MA, US
IPC
H01L 021/20
View Original Source

Citations: 9

  1. Eugene Fitzgerald
    Matthew T Currie, Anthony J Lochtefeld, Christopher W Leitz, Eugene A Fitzgerald: Methods of fabricating semiconductor devices having strained dual channel layers. AmberWave Systems Corporation, Goodwin Procter, July 28, 2009: US07566606 (9 worldwide citation)
  2. Eugene Fitzgerald
    Minjoo L Lee, Christopher W Leitz, Eugene A Fitzgerald: Structure and method for a high-speed semiconductor device having a Ge channel layer. Massachusetts Institute of Technology, Goodwin Procter, May 7, 2013: US08436336
  3. Jean Francois Damlencourt, Yves Morand, Laurent Clavelier: based zones with different contents in Ge on a same substrate by condensation of germanium, Ge, Method for producing Si. Commissariat a l Energie Atomique, STMicroelectronics, Oblon Spivak McClelland Maier & Neustadt L, October 6, 2009: US07598145 (37 worldwide citation)
  4. Narayanan Balasubramanian, Richard Hammond: Method to reduce junction leakage current in strained silicon on silicon-germanium devices. Agency for Science Technology and Research, Saile Ackerman, Stephen B Ackerman, September 16, 2008: US07425751 (7 worldwide citation)
  5. Cécile Aulnette, Frédéric Dupont, Carlos Mazuré: Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same. S O I Tec Silicon on Insulator Technologies, Winston & Strawn, June 19, 2007: US07232743 (4 worldwide citation)
  6. Derick J Wristers, David Wu, Hormuzdiar E Nariman: adjustment in SiGe system for leakage optimization, Selective P-channel V. Advanced Micro Devices, McDermott Will & Emery, August 7, 2007: US07253045 (3 worldwide citation)
  7. Matthew T Currie, Anthony J Lochtefeld: Methods for preserving strained semiconductor substrate layers during CMOS processing. AmberWave Systems Corporation, Goodwin Procter, August 26, 2008: US07416909
  8. Matthew T Currie, Anthony J Lochtefeld: Methods for preserving strained semiconductor substrate layers during CMOS processing. AmberWave Systems Corporation, Goodwin Procter, April 24, 2007: US07208332
  9. Benjamin Vincent, Laurent Clavelier, Jean Francois Damlencourt: Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step. Commissariat a l Energie Atomique, Pearne & Gordon, August 2, 2011: US07989327

References: 81 (view full list)

  1. Eugene Fitzgerald
    Eugene A Fitzgerald: Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization. Massachusetts Institute of Technology, Samuels Gauthier & Stevens, August 22, 2000: US06107653 (138 worldwide citation)
  2. Eugene Fitzgerald
    Eugene A Fitzgerald: Buried channel strained silicon FET using a supply layer created through ion implantation. AmberWave Systems Corporation, Testa Hurwitz & Thibeault, April 29, 2003: US06555839 (133 worldwide citation)
  3. Eugene Fitzgerald
    Eugene A Fitzgerald: Buried channel strained silicon FET using a supply layer created through ion implantation. Amberwave Systems Corporation, Testa Hurwitz & Thibeault, July 15, 2003: US06593191 (82 worldwide citation)
  4. Eugene Fitzgerald
    Eugene A Fitzgerald, Nicole Gerrish: Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs. AmberWave Systems Corporation, Testa Hurwitz & Thibeault, November 18, 2003: US06649480 (60 worldwide citation)
  5. Jon J Candelaria: Enhanced mobility MOSFET device and method. Motorola, Kevin B Jackson, November 4, 1997: US05683934 (300 worldwide citation)
  6. Seiji Imai, Yoshiko Hiraoka, Atsushi Kurobe, Naoharu Sugiyama, Tsutomu Tezuka: Si-SiGe semiconductor device and method of fabricating the same. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, December 8, 1998: US05847419 (246 worldwide citation)
  7. Bruce A Ek, Subramanian S Iyer, Philip M Pitner, Adrian R Powell, Manu J Tejwani: Substrate for tensilely strained semiconductor. International Business Machines Corporation, David Aker, October 24, 1995: US05461243 (219 worldwide citation)
  8. Leonard Forbes, Wendell P Noble: High density flash memory. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, November 7, 2000: US06143636 (197 worldwide citation)
  9. Jack Oon Chu, Khalid EzzEldin Ismail: Strained Si/SiGe layers on insulator. International Business Machines Corporation, Robert M Trepp, May 9, 2000: US06059895 (184 worldwide citation)
  10. Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A Ott: High speed composite p-channel Si/SiGe heterostructure for field effect devices. International Business Machines Corporation, Robert M Trepp, February 26, 2002: US06350993 (178 worldwide citation)