06914324 is referenced by 73 patents and cites 164 patents.

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

Title
Memory expansion and chip scale stacking system and method
Application Number
10/453398
Publication Number
6914324 (B2)
Application Date
June 3, 2003
Publication Date
July 5, 2005
Inventor
Jeff Buchle
Austin
TX, US
James Douglas Wehrly Jr
Austin
TX, US
David L Roper
Austin
TX, US
James Wilder
Austin
TX, US
James W Cady
Austin
TX, US
Russell Rapport
Austin
TX, US
Agent
Andrews Kurth
Assignee
Staktek Group
TX, US
IPC
H01L 023/02
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