06897565 is referenced by 59 patents and cites 154 patents.

A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Title
Stacked packages
Application Number
10/267450
Publication Number
6897565 (B2)
Application Date
October 9, 2002
Publication Date
May 24, 2005
Inventor
Craig S Mitchell
San Jose
CA, US
Young Gon Kim
Cupertino
CA, US
David Gibson
Lake Oswego
CA, US
L Elliott Pflughaupt
Los Gatos
CA, US
Agent
Lerner David Littenberg Krumholz & Mentlik
Assignee
Tessera
CA, US
IPC
H01L 023/48
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