06888741 is referenced by 2 patents and cites 7 patents.

Disclosed herein is a 4T (four transistor) SRAM cells. Stability, fabrication and integration density advantages as well as a high degree of soft error immunity with small and potentially tailorable write delay penalty may potentially be available in a memory cell by providing a source of pull down current through leakage of stabilizing capacitors, pass gate transistor leakage/off current, or a combination thereof. The source of pull down current allows omission of active pull down devices in a four transistor memory cell circuit to substantially reduce memory cell size or footprint while providing levels of soft error immunity comparable to or exceeding that of known 6T memory cell designs fabricated at comparable minimum feature size regimes and avoiding the expected increase of soft error rates as minimum feature size and/or number of circuit elements is reduced.

Title
Secure and static 4T SRAM cells in EDRAM technology
Application Number
10/223198
Publication Number
6888741 (B2)
Application Date
August 16, 2002
Publication Date
May 3, 2005
Inventor
Robert C Wong
Poughkeepsie
NY, US
Agent
Ira D Blecker
Whitham Curtis & Christofferson P C
Assignee
International Business Machines Corporation
NY, US
IPC
G11C 011/00
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