06888372 is referenced by 8 patents and cites 4 patents.

A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second address registers and a second data registers. At least one look-up table is stored in the RAM block. First programmable logic circuitry is programmed to operate as a shift register with multiple tap outputs to multiple first address registers. Second programmable logic circuitry is programmed to operate as accumulate circuitry which includes a multi-bit input coupled to multiple first data registers and includes an accumulator output.

Title
Programmable logic device with soft multiplier
Application Number
10/326652
Publication Number
6888372 (B1)
Application Date
December 20, 2002
Publication Date
May 3, 2005
Inventor
Asher Hazanchuk
Sunnyvale
CA, US
Agent
Morrison & Foerster
Assignee
Altera Corporation
CA, US
IPC
H03K 019/177
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