06853578 is referenced by 9 patents and cites 7 patents.

A single bit line, pulse-operated memory cell. The memory cell includes a first and second inverter, write access and feedback-control transistors, and read access transistor and read buffer transistors. The output of the first inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of the first inverter through the channel of the feedback-control transistor. The write access and feedback-control transistors are opposite types, and their gates are connected together so that when the feedback control transistor is on the write-access transistor is off and visa versa. Writing the cell thus avoids contending the with the on-transistor of the second inverter. The output of the cell is sensed by the gate of the buffer transistor and coupling the output of the buffer transistor through the read access transistor to the read output line.

Title
Pulse driven single bit line SRAM cell
Application Number
10/101075
Publication Number
6853578 (B1)
Application Date
March 18, 2002
Publication Date
February 8, 2005
Inventor
Jianbin Wu
Fremont
CA, US
Feng Chen
Fremont
CA, US
Wei Zhang
Sunnyvale
CA, US
Agent
Dechert
Anthony Diepenbrock III
Assignee
Piconetics
CA, US
IPC
G11C 007/00
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