06839828 is referenced by 145 patents and cites 6 patents.

There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address information. A parallel vector unit, coupled to the register files, includes functional units configurable to operate in a vector operation mode and a scalar operation mode. The vector unit includes an apparatus for tightly coupling the functional units to perform an operation specified by a current instruction. Under a vector operation mode, the vector unit performs, in parallel, a single vector operation on a plurality of data elements. The operations performed on the plurality of data elements are each performed by a different functional unit of the vector unit. Under a scalar operation mode, the vector unit performs a scalar operation on a data element received from the register files in a functional unit within the vector unit.

Title
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
Application Number
9/929805
Publication Number
6839828 (B2)
Application Date
August 14, 2001
Publication Date
January 4, 2005
Inventor
Martin Edward Hopkins
Chappaqua
NY, US
Harm Peter Hofstee
Austin
TX, US
Michael Karl Gschwind
Mohegan Lake
NY, US
Agent
Louis J Percello
Keusey Tutunjian & Bitetto P C
Assignee
International Business Machines Corporation
NY, US
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