06831893 is referenced by 211 patents.

A network interface that processes data packets transmitted on a network is provided. The network interface includes a first data path, a second data path, a header processor, a classifier unit, and a plurality of packet processors. The first data path unit inputs downstream data packets transmitted downstream on the network, and the second data path unit inputs upstream data packets transmitted upstream on the network. The header processor inputs data packet headers of the downstream and upstream data packets from the first and second data path units and classifies the downstream and upstream data packets by comparing the headers with predetermined rules. The classifier unit also inputs the data packet headers from the first and second data path units and evaluates the headers determine flows corresponding to the downstream and upstream data packets. The classifier unit selects a first packet processor to process both the downstream and upstream data packets corresponding to a first flow and instructs the first and second data path units to output the data packets, which correspond to the first flow, to the first packet processor. Similarly, the classifier unit selects a second packet processor to process both the downstream and upstream data packets corresponding to a second flow and instructs the first and second data path units to output the data packets, which correspond to the second flow, to the second packet processor. The classifier is further capable of balancing loads between the packet processors based on the effective load on each such packet processor.

Title
Apparatus and method for wire-speed classification and pre-processing of data packets in a full duplex network
Application Number
9/541598
Publication Number
6831893 (B1)
Application Date
April 3, 2000
Publication Date
December 14, 2004
Inventor
Ofer Weil
Aderet
US
Sagi Ravid
Zichron Yakov
US
Michael Ben Nun
Ramat Hasharon
US
Agent
Sughrue Mion PLLC
US
Assignee
P Cube
US
IPC
G08C 15/00
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