06825529 is referenced by 141 patents.

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

Title
Stress inducing spacers
Application Number
10/318602
Publication Number
6825529 (B2)
Application Date
December 12, 2002
Publication Date
November 30, 2004
Inventor
Xavier Baie
Wavre
US
Jack A Mandelman
Flat Rock
NC, US
Bruce B Doris
Brewster
NY, US
Omer H Dokumaci
Wappingers Falls
NY, US
Dureseti Chidambarrao
Weston
CT, US
Agent
Eugene I Shkurko
US
Jay H Anderson
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 29/76
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