06807609 is referenced by 14 patents.

A computer system is adapted to transfer write data from a central processing unit to one of a plurality of memory modules in a memory array by transferring a block of write data to a memory control logic device. The memory control logic device transfers the block of data in a plurality of data bursts interspaced by a preselected number of bus cycles. During the interspaced preselected number of bus cycles, the memory control logic device sends pending read commands to an available memory module thereby overlapping read and write operations on the memory bus, thus, lowering memory read latency.

Title
Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
Application Number
8/67262
Publication Number
6807609 (B1)
Application Date
May 25, 1993
Publication Date
October 19, 2004
Inventor
Raj Ramanujan
Leominster
MA, US
Paul J Lemmon
West Townsend
MA, US
Assignee
Hewlett Packard Development Company
TX, US
IPC
G06F 13/28
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