06772274 is referenced by 213 patents and cites 4 patents.

A flash memory system is designed to reduce inefficiencies associated with keeping track of logical block address (LBA) to physical block address (PBA) correlation or mappmg—each logical block address generated by a host digital system and associated with data when the data is sent to be stored in the flash memory system by the host digital system. The flash memory system preferably comprises at least one flash memory device having a flash memory array, the flash memory array including a plurality, of blocks for storing data and for storing (LBA to PBA) correlation, each block having a plurality of sectors, and a controller coupled to each flash memory device, the controller including a new space manager. By removing from the space manager the task of tracking correlation between the LBA and the PBA, considerable savings in manufacturing costs and logic circuit area on an integrated circuit are achieved and design flexibility attained. The new space manager continues to keep track of the flags associated with the blocks in the flash memory system. However, sufficient blocks are specifically reserved for keeping track of the (LBA to PBA) correlation of the data stored in the flash memory system and are referred to as correlation blocks. In addition, the flash memory system avoids erase-before-write operations whenever possible during the process of keeping track of (LBA to PBA) correlation.

Flash memory system and method implementing LBA to PBA correlation within flash memory array
Application Number
Publication Number
6772274 (B1)
Application Date
September 13, 2000
Publication Date
August 3, 2004
Petro Estakhri
Haverstock & Owens
Lexar Media
G06F 12/00
View Original Source