06738954 is referenced by 57 patents.

A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

Title
Method for prediction random defect yields of integrated circuits with accuracy and computation time controls
Application Number
9/636478
Publication Number
6738954 (B1)
Application Date
August 10, 2000
Publication Date
May 18, 2004
Inventor
Gustavo E Tellez
Essex Junction
VT, US
Dennis M Newns
Yorktown Heights
NY, US
Daniel N Maynard
Craftsbury Common
VT, US
Mark A Lavin
Katonah
NY, US
Alan D Dziedzic
Newburgh
NY, US
Wilm E Donath
New York
NY, US
Archibald J Allen
Grand Isle
VT, US
Agent
McGinn & Gibb PLLC
US
Agent
Richard M Kotulak Esq
US
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 17/50
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