06734461 is referenced by 192 patents and cites 11 patents.

A SiC wafer comprises a 4H polytype SiC substrate

2

in which the crystal plane orientation is substantially {03-38}, and a buffer layer

4

composed of SiC formed over this SiC substrate

2

. The {03-38} plane forms an angle of approximately 35° with respect to the axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer

6

on the buffer layer

4

. Lattice mismatching between the SiC substrate

2

and the active layer

6

is suppressed by the buffer layer

4

. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

Title
SiC wafer, SiC semiconductor device, and production method of SiC wafer
Application Number
10/70472
Publication Number
6734461 (B1)
Application Date
March 7, 2002
Publication Date
May 11, 2004
Inventor
Hiroyuki Matsunami
Yawata
US
Tsunenobu Kimoto
Kyoto
US
Hiromu Shiomi
Suita
US
Agent
McDermott Will & Emery
US
Assignee
Sumitomo Electric
US
Mitsubishi Corporation
US
Kansai Electric Power C C
US
Sixon
US
IPC
H01L 31/0312
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