06731667 is referenced by 24 patents and cites 1 patents.

A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers the modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Title
Zero-delay buffer circuit for a spread spectrum clock system and method therefor
Application Number
9/442751
Publication Number
6731667 (B1)
Application Date
November 18, 1999
Publication Date
May 4, 2004
Inventor
Joonbae Park
Seoul
US
Kyeongho Lee
Seoul
US
Agent
Fleshner & Kim
US
Assignee
AnaPass
US
IPC
H04B 1/713
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