06730589 is referenced by 12 patents and cites 11 patents.

A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (

12

) on a wafer (

10

); a step of providing a resin layer (

14

) as a stress relieving layer on the wafer (

10

), avoiding the electrodes (

12

); a step of forming a chromium layer (

16

) as wiring from electrodes (

12

) over the resin layer (

14

); a step of forming solder balls as external electrodes on the chromium layer (

16

) over the resin layer (

14

); and a step of cutting the wafer (

10

) into individual semiconductor chips; in the steps of forming the chromium layer (

16

) and solder balls, metal thin film fabrication technology is used during the wafer process.

Title
Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument
Application Number
10/254600
Publication Number
6730589 (B2)
Application Date
September 26, 2002
Publication Date
May 4, 2004
Inventor
Nobuaki Hashimoto
Suwa
US
Agent
Oliff & Berridge
US
Assignee
Seiko Epson Corporation
US
IPC
H01L 21/44
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