06704856 is referenced by 5 patents.

A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages. In the first stage, a local count is determined for each row in a local group of rows, and a global count is determined for the entire local group. Each local count is determined by counting the validity indicators associated with rows in the local group. In the second stage, a final count is determined for each row in the queue, by combining the local and global counts generated for the local group in the first stage, with global counts generated in local groups below the local group. The N rows can extend to the queue's input pipeline.

Title
Method for compacting an instruction queue
Application Number
9/465175
Publication Number
6704856 (B1)
Application Date
December 17, 1999
Publication Date
March 9, 2004
Inventor
Bruce A Gieseke
Ashland
MA, US
Daniel L Leibholz
Cambrdige
MA, US
Timothy C Fischer
Maynard
MA, US
James A Farrell
Harvard
MA, US
Assignee
Hewlett Packard Development Company
TX, US
IPC
G06F 9/30
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